The last year or so was already a wild ride for the open source instruction set architecture RISC-V, then Intel stepped in, took a top tier membership, a seat on the board, pledged to spend a billion dollars on the architecture, and began partnering with key RISC-V vendors.
RISC-V, the open-source reduced instruction set architecture that’s used for everything from accelerators and microcontrollers to CPUs and GPUs, continues to be on an accelerating roll (no pun intended). When I asked Calista Redmond, CEO of RISC-V International, the nonprofit foundation in charge of the project, to put the current state of RISC-V into a single word, she didn’t hesitate.
“Velocity,” she answered.
She said that RISC-V’s pace of growth during the last 12 months was already increasing exponentially, when in February the unthinkable happened: the world’s largest chipmaker, Intel, got on board and not only signed up as a top tier premier member (and took a seat on the foundation’s board), it gave weight to its commitment by immediately entering into partnerships with five top RISC-V vendors, and pledged to invest $1 billion in the architecture.
Intel and RISC-V
Redmond called that “perhaps one of the biggest moments in RISC-V history,” and compared it to IBM’s famous billion dollar investment in Linux in 2001, which quickly led to Linux’s dominance in data centers, at the expense of Windows and proprietary Unixes.
“I say that they’re similar because IBM had a formidable software business,” she said. “They weren’t worried about cannibalizing that. They said, ‘the future is open; the future includes “both and”, the future includes choice.’ Intel, very similarly, has its own architecture side of the house and it has a foundry side of the house. Diversifying their portfolio by including support for RISC-V was a business decision. It’s looking at the market opportunity, it’s looking at the technical fit within their portfolio, and they said, ‘you know what, “both and”.'”
Although Intel’s involvement wasn’t anticipated, it wasn’t much of a surprise, either. In January, a month before it signed on with RISC-V, it announced plans to spend $20 billion building a chip-making foundry in Ohio, in part to address the global chip shortage. In an announcement made a short time later, Intel announced that once the Ohio facility is ready for production, it will open its doors to accommodate companies needing to produce chips based on architectures other than its proprietary products, including Arm and RISC-V.
A logical next step, then, was for Intel to knock on RISC-V’s door.
Intel isn’t the only chip company making the jump from being a competitor of RISC-V to being a partner. Wave Technologies, the company behind MIPS, another reduced instruction set architecture that’s been around since 1985, announced that it was releasing two RISC-V chips, and that going forward it would be dropping its long-in-the-tooth MIPS specification in favor of RISC-V.
“MIPS completely transitioning their entire strategy over to RISC-V is huge,” Redmond said. “I mean, there’s a lot of MIPS out there, there’s a lot of similarities between what MIPS has and what RISC-V offers, and they have committed to turn their whole portfolio over, and will be coming out with a SOC by the end of the year.”
In 2018, Wave had open sourced its MIPS IP, evidently hoping at the time to bring renewed interest to the aging architecture.
How RISC-V Got Here From There
RISC-V has been gathering momentum since at least the spring of 2018, which is when RISC-V vendor SiFive caught the tech world’s attention by offering HiFive Unleashed, a RISC-V powered developers’ board, for what seemed to be the whoppingly high price of $999. Surprisingly, it sold out within a month, taking in $143,000 in the process, and within weeks numerous Linux distributions were working to make their software installable on the architecture.
That same year the data storage company Western Digital, which had previously announced it was shifting its entire product line to RISC-V, participated in SiFive’s Series C $50.6 million funding round, signed a multi-year license for SiFive’s Freedom Platform, and pledged to produce a billion RISC-V cores.
A year later, in 2019, Naveed Sherwani, who was then SiFive’s CEO, said that RISC-V-based “cellphones and laptops are two years away, and servers are five years away,” and by 2021 Mark Himelstein, CTO at RISC-V International, said that servers powered by RISC-V CPUs were already being built and deployed by Alibaba, the China-based hyperscaler that’s also a premier member of RISC-V International.
While Alibaba’s use of the architecture in servers running production workloads is something of a not-so-well-guarded secret, meaning information is scant, the company has released several RISC-V designs with impressive specs to the public under open source licenses (the vanilla RISC-V specification is released under a “permissive” license, which means that companies are free to release their own RISC-V implementations as proprietary, if they wish).
Other RISC-V News
Last September, a five-year-old RISC-V-focused startup, Ventana, emerged from stealth with an announcement that it had raised $38 million in a Series B funding round that was led by Marvel Technology Group founders Sehat Sutardja and Weili Dai, as well as other prominent semiconductor investors. Many of the investors in the company’s Series A round, held while the company was still in stealth mode, were also on board for the second round, including a “name brand” networking company.
Ventana’s emergence in RISC-V space was important, and likely had something to do with catching Intel’s interest. The startup’s founder, Balaji Baktha, has a long history in semiconductor space, both as a founder of numerous silicon-focused startups, and for the time he spent as an employee at companies such as Adaptec (now part of Microsemi) where he was VP of storage networking, and Marvell Semiconductor, where he served for more than three years as a VP and general manager.
Not long after Ventana emerged from stealth, Baktha told me that off-the-shelf RISC-V-driven devices, from servers to cell phones, was at hand.
“That moment has already started,” he said. “Go back and take a look at the latest announcement from Alibaba. Not too long ago they ported Android to RISC-V. Chrome is being ported onto RISC-V. Open notebook architectures will all be there to support this. I won’t get into any more details, but the bottom line is that in a not too distant future you’re going to see that.”
RISC-V players have also been getting their ducks in a row for taking advantage of the automotive market, which is one of the fastest growing markets for computer chips . In Feburary, not long after Intel placed its RISC-V bet, Taiwan-based Andes Technology, a supplier of RISC-V processor cores, announced that it’d been certified to be compliant with ISO 26262, which are standards for automotive functional safety processor cores.
Bubbling Beneath the Big Story
With Intel’s billion dollar involvement obviously being the biggest story involving RISC-V recently (if not ever), I asked Redmond what she thought was the second biggest RISC-V story during the last 12 months or so. She gave me what amounted to a list.
“We’ve got several things happening,” she said. “The U.S., Europe, Spain, India — all of these countries or regions have doubled down on their commitment to open hardware. They’ve publicized big numbers in each of those regions. The Ministry of Electronics and Information Technology (MeitY) in India, has committed to RISC-V and joined as a premier member. We’ve had ongoing support from China Academy of Sciences as well — they are some of our best global open source citizens because they have committed an entire team to helping us handle some of the technical pieces that we need to get ratified. Spain has just announced more than $12 billion in their semiconductor investment plans that includes RISC-V. That was perhaps the first time I had a president of a country tweet about RISC-V, which was pretty cool.
“We’ve had a lot of what I would call public-private sector engagement and investment,” she added. “DARPA has been a fan of RISC-V since the beginning, so that’s been very big this year. I would include key announcements from MIPS alongside different companies that are hitting some of the price performance points typical of what you would find in the data center. Esperanto has their highly performant processes that they’re doing, and there’s a lot of progress in HPC, as well. A lot of these are testament to RISC-V across the entire compute spectrum.”
RISC-V has a couple of large conferences upcoming in 2022. The first, RISC-V Summit China, is an online event (with an in-person component at venues around China) that will stream in both English and Chinese August 24-26. The other, RISC-V Summit 2022, is an in-person event that will be held in San Jose, California on December 13-15.