Risc-V Summit North America 2025

This October 22–23, RISC-V Summit North America 2025 will bring the global RISC-V community together in Santa Clara for two packed days of keynotes, technical sessions, workshops, and an expo floor buzzing with demos. If open standard hardware is (or could be) your thing, this is your chance to be in the room where it happens.
If there was ever an example of RISC-V’s place at the heart of modern computing, this is it. Just look at who’s confirmed to take center stage so far: Clayton Turner, Director of NASA’s Langley Research Center; Martin Dixon, Engineering Director at Google; alongside trailblazers like RISC-V founder Krste Asanović and Microchip’s Ted Speers and a host of well-known faces from across the global community.

But RISC-V Summit North America isn’t just about sitting and listening. An architecture built on open standards thrives on open discussion. From panel discussions to workshops, poster presentations to our extensive exhibition hall and developer zone, we’re bringing the ecosystem together in Santa Clara to network, share breakthroughs, swap ideas, and shape the next wave of silicon innovation.

Why Should I Attend?

Whether you’re a chip designer, software developer, VC startup, or global tech leader, there’s something for you at RISC-V Summit North America 2025. We live in a world of remote calls and virtual meetups, but there’s still no substitute for being in the same room. That’s why the Summit matters:

• Collaboration is faster face-to-face. An expo hall demo or quick hallway chat can resolve what would take weeks over email.
• Inspiration is contagious. Hearing pioneers speak, seeing demos live, sharing meals — it all fuels your own ideas.
• Connections are stronger. A handshake and shared conversation builds trust in a way that Zoom simply can’t.
• If you care about where open computing is headed, RISC-V Summit North America 2025 is the place to be. Don’t just read the coverage afterwards — help us shape it.

And if you’re new to the RISC-V ecosystem and don’t know where to start, join us on Tuesday, October 21st at 9 am for RISC-V 101: A free session featuring RISC-V International CEO Andrea Gallo and Jeffrey Osier-Mixon, Senior Principal Community Architect within the Office of the CTO at Red Hat.

Whether you’re curious about RISC-V or looking to deepen your understanding, it’ll give you a solid grounding in the ISA before heading into the main Summit. Registration is separate from the RISC-V Summit and can be completed here.

Summit Tracks

The RISC-V Summit North America is structured around dedicated tracks, each focusing on a core area of the ecosystem. This format ensures you can dive deep into the topics most relevant to your role, helping you maximize learning, networking, and value from every session throughout the event. You can build and track your own agenda in the Sched app.

• Artificial Intelligence (AI): Discover how RISC-V unlocks AI, from tiny edge devices to powerful accelerators, with strategies to differentiate and scale. We’ve built this track for chip and system architects, ML engineers, software leads, and product owners shaping AI roadmaps.
• Datacenter / HPC: Move workloads faster and cheaper on open platforms. This track shares the latest on RISC-V servers, accelerators, and ecosystem readiness – as well as the latest HPC and supercomputing research from academia. It’s ideal for CTOs, platform owners, hyperscalers, OS vendors, and researchers driving cloud or supercomputing strategy and technology.
• Design and Verification: Turn ideas into silicon with confidence. Learn proven flows, best practices, and war stories that de-risk schedules and raise quality. Targeted at RTL designers, DV leads, EDA partners, and program managers chasing first-silicon success.
• Global Adoption: See how organizations and countries are scaling with RISC-V: strategies, case studies, and partnership models you can reuse. Perfect for executives, policymakers, investors, and program leaders building resilient supply chains and open computing initiatives.
• ISA and Processors: Get the inside track on the RISC-V ISA and next-gen cores: what’s shipping, what’s coming, and why it matters. CPU architects, implementers, contributors, and product planners making roadmap and investment decisions – this is the track for you.
• Security: Build trust from silicon to software. This track spotlights secure design patterns, memory safety techniques (CHERI), and certification paths for real products. We’ve geared this track towards security architects, firmware leaders, auditors, and CISOs responsible for safety, compliance, and resilience.
• Software: Bring your stack to life on RISC-V. Learn the state of kernels, toolchains, libraries, and containers—plus the practices that speed porting and performance. Suited to maintainers, distro builders, SDK teams, app developers, and DevOps.

RISC-V Developer Workshops

On Wednesday, October 22, 2025, hands-on developer workshops run alongside the summit as a separately ticketed program. Two concurrent tracks—hardware and software—deliver expert-led labs, practical guidance, and access to instructors you won’t find anywhere else.

Whether you’re architecting silicon or tuning toolchains, you’ll leave with working knowledge and reproducible artifacts.

Highlights include:

• Designing a RISC-V application processor
• Verifying your RISC-V application processor
• Optimizing designs for FPGAs
• Porting software to RISC-V hardware
• Optimizing software for RISC-V Vector (RVV)
• Building Yocto images

Capacity is limited to keep sessions intimate, so reserve a seat early to guarantee instructor attention and bench time. Learn about developer workshops here.